Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer
Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer
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DOI：
10.1109/tim.2022.3193202
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发表时间：
2022
影响因子：
5.6
通讯作者：
Longjie Zhong;Shubin Liu;Donglai Xu
中科院分区：
文献类型：
--
作者：
Longjie Zhong;Shubin Liu;Donglai Xu
Microelectromechanical system (MEMS) capacitive accelerometer for the Internet of Things applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout structure instead of charge control readout structure is preferred for low cost. However, the voltage control readout structure suffers from low power efficiency [in terms of figure of merit (FoM)] due to significant parasitic-capacitance-induced noise. In this article, the correlated double amplifying (CDA) technique is proposed to reduce the noise of the voltage control readout circuit with high power efficiency. Although traditional correlated double sampling (CDS) technique can also be used in readout circuit to reduce the parasitic-capacitance-induced noise, it sacrifices driving ability and bandwidth of the readout circuit, while CDA does not. The CDA technique adopts correlated amplifying to reduced noise without significant increase of power consumption. Thus, CDA technique leads to higher power efficiency. The CDA technique is demonstrated in a fully differential readout circuit fabricated in a 0.18-um CMOS process and tested with a sensing element from a commercial MEMS accelerometer. The measurement results show that noise floor of the readout circuit is $0.5~ \mathrm {aF}/\!\surd {\mathrm {Hz}}$ and the noise floor of the whole system is $112 ~\mathrm {ug}/\!\surd {\mathrm {Hz}}$ , with a power consumption of $139~ \mu \text{W}$ and a bandwidth of 12.5 kHz. The full input range of ±4 g, an FoM1 of 80 pJ, and an FoM2 of $254 ~\mathrm {uW}{\cdot }{\mathrm {ug/Hz}}$ are achieved.
Microelectromechanical system (MEMS) capacitive accelerometer for the Internet of Things applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout structure instead of charge control readout structure is preferred for low cost. However, the voltage control readout structure suffers from low power efficiency [in terms of figure of merit (FoM)] due to significant parasitic-capacitance-induced noise. In this article, the correlated double amplifying (CDA) technique is proposed to reduce the noise of the voltage control readout circuit with high power efficiency. Although traditional correlated double sampling (CDS) technique can also be used in readout circuit to reduce the parasitic-capacitance-induced noise, it sacrifices driving ability and bandwidth of the readout circuit, while CDA does not. The CDA technique adopts correlated amplifying to reduced noise without significant increase of power consumption. Thus, CDA technique leads to higher power efficiency. The CDA technique is demonstrated in a fully differential readout circuit fabricated in a 0.18-um CMOS process and tested with a sensing element from a commercial MEMS accelerometer. The measurement results show that noise floor of the readout circuit is $0.5~ \mathrm {aF}/\!\surd {\mathrm {Hz}}$ and the noise floor of the whole system is $112 ~\mathrm {ug}/\!\surd {\mathrm {Hz}}$ , with a power consumption of $139~ \mu \text{W}$ and a bandwidth of 12.5 kHz. The full input range of ±4 g, an FoM1 of 80 pJ, and an FoM2 of $254 ~\mathrm {uW}{\cdot }{\mathrm {ug/Hz}}$ are achieved.