Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology
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开路缺陷暴露的库单元表征：系统方法
DOI：
10.1109/itc44170.2019.9000154
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
A. Chatterjee
中科院分区：
文献类型：
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作者：
Sujay Pandey;Sanya Gupta;L. MadhuSudhan;S. Natarajan;Arani Sinha;A. Chatterjee
确保高级CMOS技术节点的高缺陷覆盖范围一直是IC测试行业的主要挑战。传统的测试方法使用断层模型（例如卡住和过渡断层），以及设计网表的原始登机口级抽象被证明是在这些净学士使用的标准单元格中检测开路和短路缺陷的不足。使用单模式和两种模式测试的细胞感测试（CAT）的最新进展表明，工业IC设计中此类缺陷的覆盖率增加。但是，在库中所有单元格的缺陷表征的仿真开销实际上限制了被探索的缺陷大小的大小。此外，某些效果（例如电池内的电荷共享）可能需要进行超过两个时间范围的测试才能暴露出细微的缺陷。这项工作通过仿真确定了某些尺寸的缺陷，这些缺陷可能无法通过当前方法发现。然后，它提出了一种用于细胞表征的算法方法，该方法可以更快地识别基于缺陷模拟方法的细胞输入刺激。
Ensuring high defect coverage for advanced CMOS technology nodes has been a major challenge for the IC test industry. Traditional test methods using fault models such as stuck-at and transition faults with a primitive gate-level abstraction of design netlists have been shown to be inadequate for detecting open-circuit and short-circuit defects within instances of standard cells used in those netlists. Recent advances in Cell-Aware Test (CAT) using single pattern and two pattern tests have demonstrated increased coverage of such defects in industrial IC designs. However, the simulation overhead of defect characterization for all the cells in a library practically limits the size of defects that are explored to large magnitudes. Furthermore, certain effects such as charge sharing within cells can necessitate tests that span more than two time frames to expose subtle defects. This work, through simulation, identifies defects of certain sizes that can go undetected by current methods. It then proposes an algorithmic approach towards cell characterization that can result in faster identification of cell input stimuli vis-a-vis a defect simulation based method.