Security strategy of powered-off SRAM for resisting physical attack to data remanence
Security strategy of powered-off SRAM for resisting physical attack to data remanence
复制标题
断电SRAM抵御数据剩磁物理攻击的安全策略
DOI：
10.1088/1674-4926/30/9/095010
复制
发表时间：
2009-09-01
影响因子：
5.1
通讯作者：
Wang Weixu
中科院分区：
文献类型：
--
作者：
Yu Kai;Zou Xuecheng;Wang Weixu
This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25 μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.
