High-Voltage CMOS ESD and the Safe Operating Area
High-Voltage CMOS ESD and the Safe Operating Area
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DOI：
10.1109/ted.2009.2022698
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发表时间：
2009-06
影响因子：
3.1
通讯作者：
A. Walker;H. Puchner;S. Dhanraj
中科院分区：
文献类型：
--
作者：
A. Walker;H. Puchner;S. Dhanraj
已建立的用于测试智能功率CMOS中高压引脚的ESD鲁棒性的方法可能会导致错误的结果。本文研究了LDNMOS和某些类型的SCRLDMOS（SCR嵌入LDNMOS）的高压钳位安全工作区崩溃由于触发电压（V t1）走在传输线脉冲（TLP）对应的泄漏电流增加低于I t2。对于第一次，V t1作为TLP脉冲的数量和它们的幅度的函数的演变示出。此外，一些高电压钳位电路本身是强大的，在某些电路环境中，存在高电容。通过失效分析，已经建立了这种泄漏增强和击穿电压进入的物理机制，这与可能由金属迁移辅助的熔体细丝生长一致。一个简单的唯象模型提出来解释这种行为。最后，通过简单的布局变化，以避免这种V t1崩溃在SCRLDMOS的能力。
Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I t2. For the first time, the evolution of V t1 as a function of the number of TLP pulses and their magnitude is shown. Furthermore, some high-voltage clamps that are robust on their own are shown to walk-in in certain circuit environments that present high capacitance. The physical mechanism for this leakage enhancement and trigger-voltage walk-in has been established through failure analysis to be consistent with melt filament growth perhaps aided by metal migration. A simple phenomenological model is proposed to explain this behavior. Finally, the ability to avoid such V t1 collapse in SCRLDMOS through simple layout changes is shown.