Bit-level perceptron prediction for indirect branches
Bit-level perceptron prediction for indirect branches
复制标题
间接分支的位级感知器预测
DOI：
10.1145/3307650.3322217
复制
发表时间：
2019
期刊：
影响因子：
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通讯作者：
Jiménez, Daniel A.
中科院分区：
文献类型：
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作者：
Garza, Elba;Mirbagher-Ajorpaz, Samira;Khan, Tahsin Ahmad;Jiménez, Daniel A.
现代软件使用间接分支用于各种目的，包括但不限于虚拟方法调度和switch语句的实现。由于间接分支的目标地址在执行前无法确定，高性能处理器依赖于高精度的间接分支预测技术来降低控制风险，本文提出了一种新的间接分支预测方案，该方案在比特级预测目标地址。使用一系列基于感知器的预测器，我们的预测器根据分支历史中的相关性预测单个分支目标地址位。我们的评估表明，这种新的分支目标预测器是有竞争力的国家的最先进的分支目标预测器在同等的硬件预算。例如，在包括SPEC和移动的应用程序的一组工作负载上，我们的预测器实现了每1000条指令0.183个误预测的误预测率，而最先进的ITTAGE预测器为0.193，基于VPC的间接预测器为0.29。
Modern software uses indirect branches for various purposes including, but not limited to, virtual method dispatch and implementation of switch statements. Because an indirect branch's target address cannot be determined prior to execution, high-performance processors depend on highly-accurate indirect branch prediction techniques to mitigate control hazards.This paper proposes a new indirect branch prediction scheme that predicts target addresses at the bit level. Using a series of perceptron-based predictors, our predictor predicts individual branch target address bits based on correlations within branch history. Our evaluations show this new branch target predictor is competitive with state-of-the-art branch target predictors at an equivalent hardware budget. For instance, over a set of workloads including SPEC and mobile applications, our predictor achieves a misprediction rate of 0.183 mispredictions per 1000 instructions, compared with 0.193 for the state-of-the-art ITTAGE predictor and 0.29 for a VPC-based indirect predictor.