Feasibility of Cascadable Plasmonic Full Adder
Feasibility of Cascadable Plasmonic Full Adder
复制标题
DOI：
10.1109/jphot.2019.2932262
复制
发表时间：
2019-08-01
影响因子：
2.4
通讯作者：
Ota, Masashi
中科院分区：
文献类型：
--
作者：
Fukuda, Mitsuo;Watanabe, Rya;Ota, Masashi
提出了一种等离子体激元可叠加全加器的概念和结构，其逻辑运算是通过表面等离子体激元的干涉实现的，其电路仅由单模和多模等离子体激元波导构成。该全加器是通过使用互补的金属-氧化物-半导体兼容工艺对沉积在金属膜上的SiO2膜进行图案化而制造的，除了金属材料之外。通过形成辐射端口从波导排出干涉之后存在的冗余表面等离子体，并且在电路中形成金属凸块以防止杂散光与波导重新耦合。的逻辑操作的电路的三维有限差分时域方法的数值确认，和表面等离子体激元强度之间的差异逻辑电平“0”和“1”的数值估计为1.5 dB，即使在最坏的情况下。这些模拟实验证实了一些输入信号模式，使用扫描近场显微镜，和表面等离子体激元强度分布监测吻合良好。
The concept and configuration of a plasmonic cascadable full adder are proposed, whose logic operation is carried out by interference of surface plasmons and whose circuits are formed only with single- and multiple-mode plasmonic waveguides. This full adder is fabricated by patterning a SiO2 film deposited on a metal film using complementary metal-oxide-semiconductor-compatible processes except for the material of metal. The redundant surface plasmons present after interference are drained from the waveguides by forming radiation ports, and metal bumps are formed in the circuits to prevent stray light recoupling with the waveguides. The logic operation of the circuits is numerically confirmed by the three-dimensional finite-difference time domain method, and the difference in surface plasmon intensity between logic level "0" and "1" is numerically estimated to be 1.5 dB even for the worst case. These simulations were experimentally confirmed for some input signal patterns using scanning near-field microscopy, and the surface plasmon intensity distributions monitored coincide well with those simulated.