Design Trade-offs in SHA-3 Multi-Message Hashing on FPGAs
Design Trade-offs in SHA-3 Multi-Message Hashing on FPGAs
复制标题
FPGA 上 SHA-3 多消息哈希的设计权衡
DOI：
10.1109/tencon.2014.7022311
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Shuichi Ichikawa
中科院分区：
文献类型：
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作者：
Yusuke Ayuzawa;Naoki Fujieda;Shuichi Ichikawa
哈希函数被广泛用于检查数据是否正确传输。Hashcak是一个重要的哈希函数，在2012年被选为SHA-3。在本文中，我们提出并评估优化的FPGA实现的多消息散列的spreadcak。我们的优化包括各种流水线组织、部分计算的重定时以及DSP单元的使用。根据评估结果，我们的实现在Xilinx Virtex-5 FPGA上的吞吐量/面积比之前的实现高出52%。虽然上述设计采用了支持逐位XOR的高级DSP单元，但即使在具有更简单乘法加法器的Spartan-6上也实现了20%的改进。
Hash functions are widely used to check whether the data are correctly transferred. Keccak is an important hash function that was selected as SHA-3 in 2012. In this paper, we propose and evaluate the optimized FPGA implementations of Keccak for multi-message hashing. Our optimizations include a variety of pipeline organizations, retiming of a part of the calculation, and the use of DSP units. According to the evaluation results, our implementation exhibited 52% higher throughput/area than the previous one on a Xilinx Virtex-5 FPGA. Although the above design adopted advanced DSP units that support bitwise XOR, 20% improvement was achieved even on a Spartan-6 with simpler multiply-adders.