Thinking outside of the chip
Thinking outside of the chip
复制标题
跳出芯片思考
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
John Park
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文献类型：
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作者：
John Park
在芯片批量出货之前，PCB设计往往是一个瓶颈。PCB是最终产品的一个重要成本要素，它推动了在降低成本方面花费的大量时间和精力。
为了实现这些节省，PCB设计人员必须最大限度地减少层数，同时实现最佳的信号和功率性能;考虑到IC引脚的密度和连接的字面“老鼠窝”，这不是一件容易的任务。问题是IC设计人员可能没有考虑PCB布局和分线图案以及通道，从而导致设计周期更长和层太多。
了解PCB将使IC设计人员能够优化芯片I/O和块级规划，并使封装设计人员能够优化由封装引脚表示的PCB接口。同时，他们可以利用DDRx和PCIe等行业标准接口及其相应的设计限制。其结果将是一个“PCB感知”IC，从而在更短的时间内设计更少的PCB层。
本文将概述设计环境的要求，促进IC，封装和PCB跨团队协作，允许不同设计团队之间的双向数据交换。鉴于ISPD对IC的关注，我们希望让IC社区“跳出芯片”思考，深入了解封装和PCB设计挑战，并确定需要合作和进一步研究的领域。
Before a chip ships in volume, PCB design is often a bottleneck. The PCB is a significant cost element of the final product, which drives major time and effort spent on cost reduction.
To achieve these savings, the PCB designer must minimize the number of layers while achieving optimal signal and power performance; no easy task given the density of IC pins and the literal "rats nest" of connections. The problem is that the IC designer may not consider the PCB placement and breakout patterns and channels resulting in longer design cycles and too many layers.
Awareness of the PCB would enable the IC designer to optimize chip I/O & block level planning, and the package designer to optimize the PCB interface represented by the package's pin-out. At the same time, they can leverage industry standard interfaces such as DDRx and PCIe and their corresponding design constraints. The result would be a "PCB aware" IC that results in fewer PCB layers designed in less time.
This paper will outline the requirements for a design environment that promotes IC, package and PCB cross team collaboration allowing bi-directional data exchange between the different design teams. Given the IC focus of ISPD, we hope to get the IC community thinking "outside of the chip", to provide insights into package and PCB design challenges and to identify areas where collaboration and further research is needed.