Nanoimprint system development for high-volume semiconductor manufacturing the and status of overlay performance
Nanoimprint system development for high-volume semiconductor manufacturing the and status of overlay performance
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用于大批量半导体制造的纳米压印系统开发以及叠层性能的现状
DOI：
10.1117/12.2258385
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Jin Choi
中科院分区：
文献类型：
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作者：
Yukio Takabayashi;Mitsuru Hiura;Hiroshi Morohoshi;Nobuhiro Kodachi;Tatsuya Hayashi;Atsushi Kimura;Takahiro Yoshida;K. Mishima;Y. Suzaki;Jin Choi
压印光刻已被证明是复制纳米级特征的一种很有前途的技术。喷射和闪光压印光刻*(J-FIL*)涉及通过喷射技术将低粘度抗蚀剂逐场沉积和曝光到衬底上。图案掩模被放入液体中，然后液体通过毛细作用快速流入掩模中的浮雕图案。在此填充步骤之后，抗蚀剂在紫外线辐射下进行交联，然后移除掩膜，在衬底上留下图案化的抗蚀剂。有许多标准来决定一项特定的技术是否已经准备好用于晶片制造。列表中包括重叠、吞吐量和缺陷率。最苛刻的设备现在需要比4纳米3西格玛更好的覆盖层。压印工具的产量目标通常为每小时80个晶片。相对于满足半导体器件生产中的拥有成本(COO)要求，缺陷和掩模寿命起着重要作用。本白皮书的目的是报告吞吐量和缺陷工作的状态，并描述在解决高级设备的覆盖方面取得的进展。为了解决高阶校正问题，引入了一种高阶失真校正(HODC)系统。详细描述了对掩模应用放大驱动和对晶片进行温度校正的组合，并给出了校正K7、K11和K17失真以及实际器件晶片上的失真的实例。
Imprint lithography has been shown to be a promising technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput and defectivity. The most demanding devices now require overlay of better than 4nm, 3 sigma. Throughput for an imprint tool is generally targeted at 80 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. In order to address high order corrections, a high order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask, and temperature correction to the wafer is described in detail and examples are presented for the correction of K7, K11 and K17 distortions as well as distortions on actual device wafers.