Dynamic and leakage power reduction of ASICs using configurable threshold logic gates
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates
复制标题
使用可配置阈值逻辑门降低 ASIC 的动态功耗和泄漏功耗
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
S. Vrudhula
中科院分区：
文献类型：
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作者：
Jinghua Yang;Joseph Davis;Niranjan S. Kulkarni;Jae;S. Vrudhula
本文演示了一种计算ASIC中使用的逻辑函数的非传统方法，以及一种使用新单元的标准单元ASIC技术映射的全自动方法。该方法在不牺牲设计性能的情况下，显著降低了功耗、泄漏、面积和线长。这种方法的核心是一个可配置的阈值逻辑门。使用这样的门的标准单元库，一个新的技术映射算法应用于自动转换成一个传统的逻辑门和阈值门的最佳组合的一个给定的网表。映射算法是基于逻辑分解的布尔函数到特定的阈值函数。这种方法被用来制造一个32位有符号的2级华莱士树乘法器在65纳米LP技术。模拟和芯片的乘法器的测量结果表明，在30%的开关活动，24%的核心面积，45%的低线长和50%的低泄漏，而没有任何性能下降的动态功耗提高了33%，相比功能等效，传统的标准单元实现。对于FIR滤波器、32位MIPS、128位AES加密电路和浮点乘法器示出了类似的结果。
This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant reduction in power, leakage, area and wire-length, without sacrificing performance of the design. At the heart of this approach is a configurable threshold logic gate. Using a standard cell library of such gates, a new technology mapping algorithm is applied to automatically transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. The mapping algorithm is based on logic decomposition of Boolean functions into specific threshold functions. This approach was used to fabricate a 32-bit signed 2-stage Wallace-Tree multiplier in a 65-nm LP technology. Simulation and chip measurement results of the multiplier show a 33% improvement in dynamic power at 30% switching activity, 24% lower core area, 45% lower wire-length and 50% lower leakage without any performance degradation, compared to a functionally equivalent, conventional standard cell implementation. Similar results are shown for a FIR filter, a 32-bit MIPS, a 128-bit AES encryption circuit and a floating-point multiplier.