System-level comparison of power delivery design for 2D and 3D ICs
System-level comparison of power delivery design for 2D and 3D ICs
复制标题
DOI：
10.1109/3dic.2009.5306539
复制
发表时间：
2009-10
期刊：
影响因子：
--
通讯作者：
Nauman H. Khan;S. Alam;S. Hassoun
中科院分区：
文献类型：
--
作者：
Nauman H. Khan;S. Alam;S. Hassoun
三维集成电路（IC）承诺高带宽、低延迟、低器件功率和小形状因子。然而，增加的器件密度和不对称封装使得3D功率输送设计成为挑战。在本文中，我们提供了2D和3D IC的功率传输的系统级比较。我们研究了各种可能影响3D IC中功率传输质量的技术。这些包括硅通孔（TSV）尺寸和间距、受控塌陷芯片连接（C4）间距以及专用和共享功率输送的组合。我们的评估系统是由四核芯片多处理器，存储器和加速引擎。这些模块中的每一个都运行代表性的SPEC基准跟踪。我们的研究结果是实用的，并为3D功率传输优化提供了明确的指导方针。更重要的是，我们表明，这是可能的，以实现2D的，甚至更好的电源质量，通过增加C4的粒度和选择合适的TSV的大小和间距。
Three-dimensional integrated circuits (IC) promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, render 3D power delivery design a challenge. In this paper, we provide a system-level comparison of power delivery for 2D and 3D ICs. We investigate various techniques that can impact the quality of power delivery in 3D ICs. These include through-silicon via (TSV) size and spacing, controlled collapse chip connection (C4) spacing, and a combination of dedicated and shared power delivery. Our evaluation system is composed of quad-core chip multiprocessor, memory, and accelerator engine. Each of these modules is running representative SPEC benchmark traces. Our findings are practical and provide clear guidelines for 3D power delivery optimization. More importantly, we show that it is possible to achieve 2D-like or even better power quality by increasing C4 granularity and selecting suitable TSV size and spacing.