Limit study of energy & delay benefits of component-specific routing
Limit study of energy & delay benefits of component-specific routing
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能量极限研究
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
A. DeHon
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文献类型：
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作者：
Nikil Mehta;Raphael Rubin;A. DeHon
随着特征尺寸向原子极限扩展，参数变化继续增加，导致延迟和能量的裕度增加。关键路径上非常慢的器件的可能性迫使设计人员增加晶体管尺寸，降低时钟速度，并在比期望更高的电压下工作，以满足时序要求。通过制造后的可配置性，fpga有机会在非关键路径上使用慢速器件，同时为关键路径选择快速器件。为了了解我们可能从特定组件映射中获得的潜在好处，我们量化了fpga在各种预测技术（45nm-12nm）和栅极尺寸上与参数变化相关的裕度，并展示了如何通过延迟感知、特定组件路由显着减少这些裕度。对于多伦多20基准集，我们表明组件特定路由可以消除变化引起的延迟裕度，并将能量最小化设计的能量减少1.42-1.98倍。我们进一步表明，这些好处随着技术规模的扩大而增加。
As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. The possibility of very slow devices on critical paths forces designers to increase transistor sizes, reduce clock speed and operate at higher voltages than desired in order to meet timing. With post-fabrication configurability, FPGAs have the opportunity to use slow devices on non-critical paths while selecting fast devices for critical paths. To understand the potential benefit we might gain from component-specific mapping, we quantify the margins associated with parameter variation in FPGAs over a wide range of predictive technologies (45nm-12nm) and gate sizes and show how these margins can be significantly reduced by delay-aware, component-specific routing. For the Toronto 20 benchmark set, we show that component-specific routing can eliminate delay margins induced by variation and reduce energy for energy minimal designs by 1.42-1.98×. We further show that these benefits increase as technology scales.