Carrier profile designing to suppress systematic Vth variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects
Carrier profile designing to suppress systematic Vth variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects
复制标题
载流子分布设计通过控制与点缺陷相关的 STI 增强掺杂剂扩散来抑制与器件布局相关的系统 Vth 变化
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
S. Satoh
中科院分区：
文献类型：
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作者：
H. Fukutome;Y. Momiyama;A. Satoh;Y. Tamura;H. Minakata;K. Okabe;E. Mutoh;K. Suzuki;A. Usujima;H. Arimoto;S. Satoh
我们直接测量到，各向异性的掺杂剂扩散到浅沟槽隔离（STI）的下沉是主要因素，导致阈值电压（Vth）的有源宽度沿着沟道方向（LOD）的nMOSFET的依赖。我们评估了拉曼光谱和3-D应力模拟的影响，STI引起的应力变化的Vth。此外，我们直接测量到掺杂剂扩散与点缺陷耦合，作为瞬态增强扩散，导致载流子分布取决于LOD。特别是，人们发现，在深源极/漏极中的多余的点缺陷增强了随机扩展边缘粗糙度，并增加了本征Vth波动的窄LOD nMOSFET。
We directly measured that anisotropic dopant diffusion into the shallow trench isolation (STI) sink was the predominant factor to cause dependence of the threshold voltage (Vth) on the active width along the channel direction (LOD) for the nMOSFETs. We evaluated by Raman spectroscopy and 3-D stress simulation effects of the STI-induced stress variation on the Vth. Moreover, we directly measured that dopant diffusions coupled with point defect, as transient enhanced diffusion, resulted in the carrier profile depending on the LOD. In particular, it was found that the excess point defect in the deep source/drain enhanced the random extension edge roughness and increased intrinsic Vth fluctuation in the narrow-LOD nMOSFET.