Time-Dependent Dielectric Breakdown of 4H-SiC/$ hbox{SiO}_{2}$ MOS Capacitors

Time-Dependent Dielectric Breakdown of 4H-SiC/$ hbox{SiO}_{2}$ MOS Capacitors
复制标题

4H-SiC/$ hbox{SiO}_{2}$ MOS 电容器随时间变化的介电击穿

DOI:
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发表时间:
2008
影响因子:
2
通讯作者:
R. Beaupre
R. Beaupre
中科院分区:
工程技术3区
文献类型:
--
作者:
M. Gurfinkel;Justin C. Horst;J. Suehle;Joseph B. Bernstein;Yoram Shapira;K. Matocha;Greg Dunne;R. Beaupre

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时间相关介质击穿(TDDB)是影响SiC基大功率器件介质层长期可靠性的主要问题之一。尽管对Si上SiO2层的TDDB进行了广泛的研究,但缺乏高质量的SiC上SiO2层的TDDB统计数据。本文提出了全面的TDDB数据的4 H-SiC电容器与SiO2栅极绝缘体收集在很宽的电场和温度范围。结果表明,在低场下,电场加速参数在2.07 ~ 3.22cm/MV之间。在高于8.5 MV/cm的电场下,电场加速参数约为4.6 cm/MV,表明在高电场应力下存在不同的失效机制。因此,寿命外推必须基于在8.5 MV/cm以下收集的失效数据。温度加速遵循阿克里尼乌斯模型,活化能约为1 eV,类似于Si上的厚SiO2层。基于这些实验数据,我们提出了一个精确的模型,考虑电场和温度加速度,面积和故障率百分位缩放的4 H-SiC MOS器件的寿命评估。它还表明,高达365摄氏度的温度可以用来加速在晶圆级的SiC器件的TDDB。
Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of SiO2 layers on Si, there is a lack of high-quality statistical TDDB data of SiO2 layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a SiO2 gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick SiO2 layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365degC can be used to accelerate TDDB of SiC devices at the wafer level.