An $80\times $ Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- $\mu $ m CMOS
An $80\times $ Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- $\mu $ m CMOS
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DOI：
10.1109/tvlsi.2014.2343244
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发表时间：
2015-08
影响因子：
2.8
通讯作者：
Horng-Yuan Shih;Sheng-Kai Lin;Po-Shun Liao
中科院分区：
文献类型：
--
作者：
Horng-Yuan Shih;Sheng-Kai Lin;Po-Shun Liao
本文提出了一种用于粗-精时间数字转换器的模拟实现的时间差分放大器。采用0.18 μ mCMOS工艺实现，在最大频率25 MHz下，可将225 ps以内的时间差放大80倍。实测最大增益误差为4.1%。在增益为80×时，实测输出均方根抖动为84.5 ps。在1.8V电源电压下，时间放大器的功耗为1.7mW.
An analog-implemented time-difference amplifier applied for coarse-fine time-to-digital converters is presented in this paper. Implemented in 0.18-μm CMOS process, a time difference within 225 ps can be amplified 80× linearly under maximum frequency of 25 MHz. Measured maximum gain error is 4.1%. Measured output rms jitter is 84.5 ps under gain of 80×. The time amplifier consumes 1.7 mW under supply voltage of 1.8 V.