On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices
On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices
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DOI：
10.1145/2629503
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发表时间：
2015-04-01
影响因子：
2.2
通讯作者：
Klein, Jacques-Olivier
中科院分区：
文献类型：
--
作者：
Chabi, Djaafar;Zhao, Weisheng;Klein, Jacques-Olivier
缩小到CMOS晶体管之外，需要结合新的计算范式和新型器件。在这种背景下，神经形态架构的发展是为了实现鲁棒和超低功耗的计算系统。忆阻纳米器件通常与这种结构相关联，以实现超高密度的高效突触。在本文中，我们研究了一个用于片上功能学习的神经启发逻辑块（NLB）的设计，并提出了学习策略。它由一组忆阻纳米器件组成，作为与神经元回路相关的突触。针对不同类型的忆阻纳米器件提出了监督学习方法，并进行了仿真，证明了用忆阻纳米器件学习逻辑函数的能力。得益于神经元电路的紧凑实现和学习过程的优化，该架构只需要少量的纳米器件和适度的功耗。
Scaling down beyond CMOS transistors requires the combination of new computing paradigms and novel devices. In this context, neuromorphic architecture is developed to achieve robust and ultra-low power computing systems. Memristive nanodevices are often associated with this architecture to implement efficiently synapses for ultra-high density. In this article, we investigate the design of a neuro-inspired logic block (NLB) dedicated to on-chip function learning and propose learning strategy. It is composed of an array of memristive nanodevices as synapses associated to neuronal circuits. Supervised learning methods are proposed for different type of memristive nanodevices and simulations are performed to demonstrate the ability to learn logic functions with memristive nanodevices. Benefiting from a compact implementation of neuron circuits and the optimization of learning process, this architecture requires small number of nanodevices and moderate power consumption.