SrTiO3 thin films by mocvd for 1 gbit DRAM application
SrTiO3 thin films by mocvd for 1 gbit DRAM application
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用于 1 GB DRAM 应用的 mocvd SrTiO3 薄膜
DOI：
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发表时间：
1995
期刊：
影响因子：
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通讯作者：
Masaji Yoshida
中科院分区：
文献类型：
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作者：
P. Lesaicherre;H. Yamaguchi;Y. Miyasaka;H. Watanabe;H. Ono;Masaji Yoshida
本文从SrTiO_3薄膜作为GB级DRAM电容介质的应用出发，详细讨论了MOCVD法制备SrTiO_3薄膜的三个重要方面：Sr（NO_3）_2-Ti（i-OC_3 H_7）_4-O_2体系的CVD反应、台阶覆盖率以及薄膜结构与电学性能的关系。首先研究了衬底温度对Sr和Ti沉积速率的影响，用于热CVD和ECR CVD SrTiO 3膜。发现在高于550°C的温度下，SrO和TiO 2的沉积分别受表面反应和气体输运的控制，而在450 ~ 600°C的温度下，SrO和TiO 2的沉积都受气体输运的控制。然后评估Sr和Ti沉积制度对SrO、TiO 2和SrTiO 3的台阶覆盖率的影响。在600°C下热CVD制备的SrO薄膜具有最好的台阶覆盖率，表明反应控制沉积与良好的台阶覆盖率之间存在联系。薄膜成分的影响。
Abstract Three important aspects of the preparation of SrTiO3 thin films by MOCVD are discussed in detail in view of the application of these films as the capacitor dielectric of Gbit-scale DRAMs: CVD reactions in the Sr(DPM)2-Ti(i-OC3H7)4-O2 system, step coverage and relations between microstructure and electrical properties. The effect of the substrate temperature on the Sr and Ti deposition rates was first investigated for thermal and ECR CVD SrTiO3 films. SrO and TiO2 deposition by thermal CVD above 550°C were found to be controlled by the surface reaction and gas transport, respectively, whereas both SrO and TiO2 deposition are controlled by gas transport for ECR CVD at 450 to 600°C. The influence of the Sr and Ti deposition regimes on the step coverage of SrO, TiO2 and SrTiO3 were then assessed. SrO films prepared by thermal CVD at 600°C exhibited the best step coverage, indicating that a relation exists between reaction controlled deposition and good step coverage. The effect of the film compositio...