Power-Gating Aware Floorplanning
Power-Gating Aware Floorplanning
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DOI：
10.1109/isqed.2007.123
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发表时间：
2007-03
期刊：
影响因子：
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通讯作者：
Hailin Jiang;M. Marek-Sadowska
中科院分区：
文献类型：
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作者：
Hailin Jiang;M. Marek-Sadowska
电源门控是一种通过关闭闲置模块来有效降低漏电功耗的技术。然而，电源门控的存在也可能带来负面影响，这些在早期设计阶段并未被考虑。忽视这些影响可能会导致设计欠佳，甚至可能使预期的节能效果化为泡影。在本文中，作者提出了一种新颖的方法来有效捕捉电源门控的影响。作者将这种方法应用于电源门控芯片的布局规划器中。实验结果表明，与不考虑电源门控的布局规划器相比，考虑电源门控的布局规划器可节省50%的去耦电容。通过插入更少的去耦电容可以节省漏电功耗，特别是当由于面积限制而使用薄氧化物去耦电容时。当面积开销被限制在芯片总面积的约19%时，该方法可将去耦电容消耗的漏电功耗从36毫瓦降低到9毫瓦。
Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects, which are not considered in the earlier design stages. Ignoring those effects may result in suboptimal designs and potentially even nullify the intended power savings. In this paper, the authors propose a novel measure to efficiently capture the power-gating effects. The authors apply this measure in a floorplanner for power-gated chips. Experimental results show that the power-gating aware floorplanner can achieve 50% decap saving compared to a floorplanner unaware of power gating. Leakage power can be saved by inserting less decap, especially when thin-oxide decap are used due to the area constraint. The approach can reduce leakage power consumed by decap from 36mW to 9mW when area overhead is limited to about 19% of the total chip area