Translation-optimized Memory Compression for Capacity
Translation-optimized Memory Compression for Capacity
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DOI：
10.1109/micro56248.2022.00073
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发表时间：
2022-10
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通讯作者：
Gagandeep Panwar;Muhammad Laghari;D. Bears;Yuqing Liu;Chandler Jearls;Esha Choukse;K. Cameron;A. Butt;Xun Jian
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作者：
Gagandeep Panwar;Muhammad Laghari;D. Bears;Yuqing Liu;Chandler Jearls;Esha Choukse;K. Cameron;A. Butt;Xun Jian
对内存的需求不断增加。许多先前的工作已经探索了硬件存储器压缩以增加有效存储器容量。然而，先前的工作以小存储器块级粒度压缩和打包/迁移数据;这在页面级虚拟地址转换之后引入了附加的块级转换。通常，地址转换的粒度越小，转换开销越高。因此，这种额外的块级转换加剧了大的和/或不规则的工作负载的公知的地址转换问题。一种有希望的解决方案是仅从冷存储器（即，最近访问较少的）页面而不节省来自热的存储器（即，最近访问的）页面（例如，保持热页未压缩）;这避免了热页的块级转换开销。然而，它仍然面临两个挑战。首先，在压缩的冷页面再次变热之后，将页面迁移到完整的4KB DRAM位置仍然在现有的虚拟地址转换之上添加另一个转换级别（尽管是页面级别，而不是块级别）。其次，仅压缩冷数据需要非常积极地压缩它们以实现高的总体存储器节省;解压缩非常积极地压缩的数据非常慢（例如，$\gt 800 ns$（假设采用业界最新的Deflate ASIC）。本文提出了翻译优化的内存容量压缩（TMCC），以解决上述两个挑战。为了解决第一个挑战，我们建议在硬件中压缩页表块，以便以软件透明的方式将压缩翻译嵌入其中，从而在页面行走期间有效地预取压缩翻译，而不是在行走后连续地获取它们。为了解决第二个挑战，我们在许多硬件配置和不同的工作负载中进行了大量的设计空间探索，以在HDL中推导和实现专用于内存的ASIC Deflate;对于内存页面，它的速度是最先进的ASIC Deflate的4倍，压缩比几乎没有牺牲。我们的评估表明，对于大型和/或不规则的工作负载，TMCC可以在不牺牲有效容量的情况下将性能提高14%，或者与最先进的硬件内存压缩相比，在不牺牲性能的情况下提供2.2倍的有效容量。
The demand for memory is ever increasing. Many prior works have explored hardware memory compression to increase effective memory capacity. However, prior works compress and pack/migrate data at a small - memory block-level - granularity; this introduces an additional block-level translation after the page-level virtual address translation. In general, the smaller the granularity of address translation, the higher the translation overhead. As such, this additional block-level translation exacerbates the well-known address translation problem for large and/or irregular workloads. A promising solution is to only save memory from cold (i.e., less recently accessed) pages without saving memory from hot (i.e., more recently accessed) pages (e.g., keep the hot pages uncompressed); this avoids block-level translation overhead for hot pages. However, it still faces two challenges. First, after a compressed cold page becomes hot again, migrating the page to a full 4KB DRAM location still adds another level (albeit page-level, instead of block-level) of translation on top of existing virtual address translation. Second, only compressing cold data require compressing them very aggressively to achieve high overall memory savings; decompressing very aggressively compressed data is very slow (e.g., $\gt 800 ns$ assuming the latest Deflate ASIC in industry). This paper presents Translation-optimized Memory Compression for Capacity (TMCC) to tackle the two challenges above. To address the first challenge, we propose compressing page table blocks in hardware to opportunistically embed compression translations into them in a software-transparent manner to effectively prefetch compression translations during a page walk, instead of serially fetching them after the walk. To address the second challenge, we perform a large design space exploration across many hardware configurations and diverse workloads to derive and implement in HDL an ASIC Deflate that is specialized for memory; for memory pages, it is 4X as fast as the state-of-the art ASIC Deflate, with little to no sacrifice in compression ratio. Our evaluations show that for large and/or irregular workloads, TMCC can either improve performance by 14% without sacrificing effective capacity or provide 2.2x the effective capacity without sacrificing performance compared to a state-of-the-art hardware memory compression for capacity.