The Characteristics of Interface Microstructures in Germanium/SiO2 Low Temperature Wafer Bonding-猫眼课题宝

DOI：

10.1149/1.3483536

发表时间：

2010-10

期刊：

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其他

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作者：

Xuan Zhang;Tianchun Ye;S. Zhuang;J. Jiao

锗/二氧化硅低温键合技术中国科学院微电子研究所，北京100029，中国上海现代光学系统重点实验室，上海科技大学现代光学系统重点实验室，中国科学院上海微系统与信息技术研究所，200050，中国，锗，由于其高电子和空穴迁移率，是一种潜在的未来半导体半导体沟道材料。它必须与硅集成，才能充分利用成熟的硅CMOS平台。然而，晶体管电流的泄漏阻碍了它的应用。因此，绝缘体上的锗(GeOI)技术，如SOI技术，是避免这一缺点的理想选择。一般来说，Ge/SiO_2/Si结构的制备技术主要有四种：(1)晶片直接键合[1]；(2)Ge凝聚技术[2]；(3)快速熔融生长技术[3]；(4)晶格匹配外延氧化物异质结[4]。方法(2)-(4)由于热膨胀或晶格常数失配的应力，必须承受高温，并可能导致高的缺陷密度。然而，在低热预算的情况下，晶片键合可以避免由于4%的晶格常数差或热应力引起的变形而产生的位错缺陷。因此，通过低温直接键合Ge/SiO_2晶片很有可能通过层转移方法实现GeOI[5]。然而，大量缺陷源于局部缺失的Ge层，阻碍了GeOI的应用[6]。本文提出了一种150℃退火后进行等离子体前处理的Ge/SiO_2原子级直接键合技术。键合界面的特征如图1所示。用150℃晶片键合退火后的横截面透射电子显微镜(XTEM)进行了表征。优化的工艺可以在Ge和SiO_2之间产生完美的原子级键合(见图1a)，而不利的工艺也可能导致局部未键合区域间距为20 nm(图1B)。一种不恰当的工艺甚至会导致锗内部的微裂纹(如图2a所示)。即使键合退火是在180℃进行的。但是，完美的结合

Germanium/SiO2 low temperature wafer bonding Xuan Xiong Zhang , Tian Chun Ye, Song Lin Zhuang, Ji Wei Jiao, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China Shanghai Key Laboratory of Modern Optical System, University of Shanghai for Science and Technology Shanghai 200093, China Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences Shanghai 200050, China, Germanium is a potential channel material for the future CMOS thanks to high mobility of electron and hole. It has to be integrated with silicon in order to sufficiently utilize mature Si CMOS platform. However, the leakage of transistor current hampers its application. Consequently, GeOI (germanium-on-insulator), such as SOI technique, is an ideal option to avoid the disadvantage. Generally speaking, the manufacturing technologies of Ge/SiO2/Si structure have main four methods: (1) direct wafer bonding[1]; (2) Ge-condensation technique[2]; (3) rapid melting growth technique[3]; (4) lattice matched epitaxial oxide heterostructure[4]. The methods (2)-(4) have to suffer high temperature and result in probably high defects density due to the stress from thermal expansion or lattice constant mismatch. However, wafer bonding in the case of low thermal budget can immunize the defects of dislocation generated by 4% lattice constant difference or distortion from thermal stress. As a result, direct wafer bonding of Ge/SiO2 through low temperature is attractive to achieve GeOI by layer transfer approach[5]. Nevertheless, a great number of defects originated from the local missing Ge layer hinders GeOI applications[6]. In this paper, we present an atomic level Ge/SiO2 direct wafer bonding technique by means of plasma pretreatment after a 150C annealing. The bonding interfaces are characterized in Fig. 1. by cross-section transmission electron microscopy (XTEM) after a 150C wafer bonding annealing. An optimal process can produce perfectly atomic level bonding between Ge and SiO2 (see Fig.1a), whereas a disadvantage process can also cause the local unbonded areas with 20nm gap (Fig. 1b). An improper process even gave rise to micro-crack within germanium (shown in Fig. 2a.) even though the bonding annealing was performed at 180C. But, the perfect bonding

The Characteristics of Interface Microstructures in Germanium/SiO2 Low Temperature Wafer Bonding

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