All-digital transmitter based on cascaded delta-sigma modulators for relaxing the analog filtering requirements
All-digital transmitter based on cascaded delta-sigma modulators for relaxing the analog filtering requirements
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基于级联 Delta-Sigma 调制器的全数字发射机，可放宽模拟滤波要求
DOI：
10.1109/mwsym.2017.8058892
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
J. Vieira
中科院分区：
文献类型：
--
作者：
Daniel C. Dinis;Arnaldo S. R. Oliveira;J. Vieira
本文将表明，不同采样率的级联δ - σ调制器可以对放松全数字发射机中使用的模拟输出滤波器的高质量因数产生相当大的影响。特别是，只需对硬件进行微小的更改，就可以显著降低噪声峰值功率。这个新概念已经在基于fpga的发射器上成功实现和验证，并与在单级中执行单比特量化的传统架构进行了比较。
In this paper it will be shown that cascading Delta-Sigma Modulators with different sampling rates can have a considerable impact in relaxing the high quality factor of the analog output filter used in All-Digital Transmitters. In particular, a significant reduction of the noise peak power can be achieved with just minor changes in the hardware. This novel concept has been successfully implemented and validated on an FPGA-based transmitter, and compared with the conventional architectures that perform a single-bit quantization into a single stage.