Buffer-trapping effects on drain lag and power compression in GaN FET
Buffer-trapping effects on drain lag and power compression in GaN FET
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DOI：
10.1002/pssc.200461311
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发表时间：
2005-05
期刊：
影响因子：
--
通讯作者：
K. Horio;K. Yonemoto
中科院分区：
文献类型：
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作者：
K. Horio;K. Yonemoto
通过二维瞬态仿真研究了 GaN MESFET 中的缓冲捕获效应。半绝缘缓冲层采用三级补偿模型，其中考虑浅施主、深施主和深受主。结果表明，当漏极电压VD升高时，漏极电流超过稳态值，而当VD降低时，漏极电流在一段时间内保持在低值，表现出漏极滞后行为。这种漏极滞后被证明是 GaN MESFET 中所谓功率压缩的一个原因。 （© 2005 WILEY-VCH Verlag GmbH & Co. KGaA，魏因海姆）
Buffer-trapping effects in a GaN MESFET are studied by two-dimensional transient simulation. A three-level compensation model is adopted for a semi-insulating buffer layer where a shallow donor, a deep donor and a deep acceptor are considered. It is shown that when the drain voltage VD is raised, the drain current overshoots the steady-state value, and when VD is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)