Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3-D NAND Flash Memory
Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3-D NAND Flash Memory
复制标题
DOI：
10.1109/ted.2022.3224420
复制
发表时间：
2023-01
影响因子：
3.1
通讯作者：
M. Raquibuzzaman;A. Milenković;B. Ray
中科院分区：
文献类型：
--
作者：
M. Raquibuzzaman;A. Milenković;B. Ray
向3D NAND技术的转变导致了包括许多页的闪存块，从而导致存储系统中的“大块”管理问题。本文通过实验探索了3-D NAND闪存块的耐久性变化，发现底层和顶层的页面比中间层的页面表现出更低的耐久性。我们发现，擦除阈值电压（${V}_{t}{）}$之间的变化是观察到的耐久性变化的根本原因。页之间耐久性的这种变化可能导致闪存的严重利用不足。为了对抗这些影响，提高整体利用率的3-D NAND闪存，我们提出了一个块内磨损均衡算法的基础上动态，增量，层意识的缩小闪存块。
A shift to 3-D NAND technology has resulted in flash memory blocks that include many pages, leading to “big-block” management issues in storage systems. This article experimentally explores endurance variability in 3-D NAND flash memory blocks and finds that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. We find that erase threshold voltage ( ${V}_{t}{)}$ variation between the layers is the root cause for the observed endurance variation. This variation in endurance among pages can cause severe underutilization of flash memory. To counter these effects and improve the overall utilization of 3-D NAND flash memories, we propose an intrablock wear-leveling algorithm based on dynamic, incremental, and layer-aware downsizing of flash memory blocks.