A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
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DOI：
10.1109/tbcas.2017.2759700
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发表时间：
2018-02-01
影响因子：
5.1
通讯作者：
Indiveri, Giacomo
中科院分区：
文献类型：
--
作者：
Moradi, Saber;Qiao, Ning;Indiveri, Giacomo
神经形态计算系统包括使用异步事件进行计算和通信的神经元网络。这种类型的表示在神经形态电子系统的带宽和功耗方面具有多种优势。但是，在电路复杂性和内存要求方面，管理大规模系统中异步事件的流量都是一项艰巨的任务。在这里，我们提出了一种新型的路由方法，该方法既采用层级和网格路由策略，并结合了异质的内存结构，以最大程度地减少内存需求和延迟，同时通过参数配置最大化编程灵活性以支持广泛的基于事件的神经网络体系结构。我们在原型多核心神经形态处理器芯片中验证了所提出的方案，该方案采用混合模拟/数字电路模拟突触和神经元动力学以及异步数字电路来管理地址 - 事实交通。我们对提出的连接方案进行了理论分析，描述用于实施此类方案的方法和电路，并表征原型芯片。最后，我们证明了神经形态处理器与卷积神经网络的使用，以高速闪烁到动态视觉传感器（DVS）的实时分类。
Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.