Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems
Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems
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DOI：
10.1109/radecs.2007.5205569
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发表时间：
2008
影响因子：
1.8
通讯作者：
Y. Yanagawa;D. Kobayashi;H. Ikeda;H. Saito;K. Hirose
中科院分区：
文献类型：
--
作者：
Y. Yanagawa;D. Kobayashi;H. Ikeda;H. Saito;K. Hirose
设计了一种扫描触发器（FF）来观察逻辑VLSI系统中的单粒子瞬态（SET）和单粒子翻转（SEU）软错误。SET和SEU软错误分别表示由锁存源自组合逻辑块的SET脉冲引起的翻转和由对FF的直接离子撞击引起的翻转。提出了一种利用扫描FF的辐照测试方法，以获得分布在逻辑VLSI系统中的每个FF的SET和SEU软错误率。一个测试芯片设计使用0.2 μ m的完全耗尽绝缘体上硅标准单元库。Verilog时序仿真验证了基本概念。所提出的扫描FF的单元级实现成本估计是合理的。
A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEU soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEU soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insulator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable.