Lockup-free instruction fetch/prefetch cache organization
Lockup-free instruction fetch/prefetch cache organization
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DOI：
10.1145/285930.285979
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发表时间：
1981-05
期刊：
影响因子：
--
通讯作者：
D. Kroft
中科院分区：
文献类型：
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作者：
D. Kroft
在过去的十年中，有很多文献描述了利用通用编程特性来获得最大命中率（请求的数据现在驻留在缓存中的概率）的各种缓存组织。几乎没有（如果有的话）可以利用：（1）高速缓存固有的双输入性质和（2）多数据引用类型中央处理器指令。无论缓存命中率有多高，缓存未命中都可能对后续缓存引用造成惩罚。这种惩罚是必须等待，直到从中央存储器接收到丢失的请求数据，并且可能需要等待缓存更新。对于上述两种情况，未命中后的高速缓存引用不需要未驻留在高速缓存中的数据的信息，因此以这种方式受到惩罚。本文提出了一种缓存组织，从根本上消除了这种损失。该高速缓存组织功能已合并到高速缓存/内存接口子系统设计中，并且该设计已实现并原型化。现有的简单指令集机器已经验证了该功能的优点；未来，更广泛、更复杂的指令集机器显然可能会占据更多优势。在原型制作之前，模拟验证了该优势。
In the past decade, there has been much literature describing various cache organizations that exploit general programming idiosyncrasies to obtain maximum hit rate (the probability that a requested datum is now resident in the cache). Little, if any, has been presented to exploit: (1) the inherent dual input nature of the cache and (2) the many-datum reference type central processor instructions. No matter how high the cache hit rate is, a cache miss may impose a penalty on subsequent cache references. This penalty is the necessity of waiting until the missed requested datum is received from central memory and, possibly, for cache update. For the two cases above, the cache references following a miss do not require the information of the datum not resident in the cache, and are therefore penalized in this fashion. In this paper, a cache organization is presented that essentially eliminates this penalty. This cache organizational feature has been incorporated in a cache/memory interface subsystem design, and the design has been implemented and prototyped. An existing simple instruction set machine has verified the advantage of this feature; future, more extensive and sophisticated instruction set machines may obviously take more advantage. Prior to prototyping, simulations verified the advantage.