A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
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DOI：
10.1109/isscc.2018.8310277
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发表时间：
2018-02
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通讯作者：
Dmytro Cherniak;Luigi Grimaldi;L. Bertulessi;C. Samori;R. Nonis;S. Levantino
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文献类型：
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作者：
Dmytro Cherniak;Luigi Grimaldi;L. Bertulessi;C. Samori;R. Nonis;S. Levantino
具有高分辨率的调频连续波（FMCW）雷达需要产生具有大峰峰值（啁啾带宽）和短调制信号周期的低相位噪声、低杂散和高度线性啁啾信号[1]。在雷达系统中，线性调频脉冲发生器的点相位噪声被转换为接收机的中频，使得难以检测到两个接近的目标，而杂散导致检测到假目标。由于这些原因，77至81 GHz频段的中程雷达应用通常要求点相位噪声在1 MHz偏移时低于− 90 dBc/Hz，杂散水平低于− 50 dBc。与三角形啁啾不同，锯齿啁啾允许减少距离检测的死区时间。然而，任何实际的调制器都需要有限的时间（空闲时间）来在锯齿结束时进行大的频率跳变，这限制了锯齿的占空比。例如，具有200 kHz速率和95%占空比的快速锯齿啁啾仅留下250 ns的空闲时间。分数N PLL可以用作啁啾调制器。遗憾的是，低相位噪声和杂散水平需要窄PLL带宽，而短空闲时间则需要宽PLL带宽。来自分频器的模控制和压控振荡器（VCO）的调谐输入的调制信号的两点注入是同时实现窄PLL带宽和快速调制的已知方法。然而，即使在该方案中，频率调制误差也主要受到两个注入路径之间的增益失配和VCO的线性度的限制[2]。在这项工作中，一个20- 24 GHz的数字bang-bang锁相环，它使用两点调制方案产生三角和锯齿啁啾信号，提出。与以往的工作不同，该结构能够产生斜率高达173 MHz/js的快速锯齿啁啾，空闲时间低于200 ns，均方根频率误差优于0.06%。两个调制路径之间的增益失配通过数字算法[5]自动校准，并且数控振荡器（DCO）的输入通过自动背景校正方案进行预失真，该方案补偿DCO非线性。
Frequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than −90dBc/Hz at 1MHz offset and spur level below −50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity.