SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures
SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures
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SOTERIA：利用工艺变化通过光子 NoC 架构增强硬件安全性
DOI：
10.1145/3195970.3196118
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
S. Pasricha
中科院分区：
文献类型：
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作者：
Sai Vineel Reddy Chittamuru;Ishan G. Thakkar;Varun Bhat;S. Pasricha
光子片上网络（PNoC）通过使用能够进行密集波分复用（DWDM）的光子波导进行信号遍历和使用微波谐振器（MR）进行信号调制来实现高带宽片上数据传输。PNoC中的硬件木马可以操纵其MR的电驱动电路，以使MR窥探来自共享光子波导中的相邻波长信道的数据。这带来了严重的安全威胁。本文提出了一种名为SOTERIA的新框架，该框架利用基于过程变化的认证签名沿着架构级增强功能来保护PNoC架构中的数据免受窥探攻击。评估结果表明，我们的方法可以显着提高基于DWDM的PNoCs的硬件安全性，最小的开销高达10.6%的平均延迟和高达13.3%的能量延迟产品（EDP）。
Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA† that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDM-based PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP).