A retrograde p-well for higher density CMOS
A retrograde p-well for higher density CMOS
复制标题
用于更高密度 CMOS 的逆行 p 阱
DOI：
10.1109/t-ed.1981.20498
复制
发表时间：
1981
影响因子：
3.1
通讯作者：
L. Walker
中科院分区：
文献类型：
--
作者：
R. Rung;C. Dell'Oca;L. Walker
本文介绍了一种新的CMOS p阱（或n阱）形成技术，即先进行深注入，然后进行简单的退火。这导致了一个倒推剖面，允许更浅的阱，p-n沟道器件间距的大幅减小（5-6 µm vs 10-15 µm），并有机会降低闩锁风险。这种技术比传统的井形成方法更有利于规模化，并具有明显更好的性能。该方法已成功地应用于线性缩小体CMOS 4K静态RAM中，证明了其可行性。
A new technique for CMOS p-well (or n-well) formation is described, making use of a deep implant followed by a brief anneal. This results in a retrograde profile, permitting a much shallower well, a large reduction in p-n channel device spacing (5-6 µm versus 10-15 µm), and an opportunity to reduce the risk of latch-up. This technique is more conducive to scaling-with the promise of significantly better performance-than conventional well formation methods. The retrograde p-well has been successfully applied to a linearly shrunk bulk CMOS 4K static RAM, demonstrating its feasibility.