An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm
An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm
复制标题
一种采用 65 nm 动态阈值误差校正的节能单次基于时间的神经网络加速器
DOI：
10.1109/jssc.2019.2914361
复制
发表时间：
2019
影响因子：
5.4
通讯作者：
C. Kim
中科院分区：
文献类型：
--
作者：
L. Everson;Muqing Liu;N. Pande;C. Kim
随着神经网络继续渗透到不同的应用领域，计算将开始从云端转移到边缘设备上，这需要快速、可靠和低功耗（LP）的解决方案。为了满足这些要求，我们提出了一个时域核心使用单次延迟测量和一个轻量级的后处理技术，动态阈值纠错（DTEC）。这种设计与传统数字实现的不同之处在于，它使用通过SRAM阵列分布的简单反相器链累积的延迟来本质上计算资源密集型乘法累积（MAC）运算。在65 nm LP CMOS中实现，我们实现了104.8 TOp/s/W的能量效率在0.7 V，3b分辨率为19.1 fJ/MAC。
As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC.