Selective Hardening in Early Design Steps
Selective Hardening in Early Design Steps
复制标题
早期设计步骤中的选择性强化
DOI：
10.1109/ets.2008.30
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
B. Becker
中科院分区：
文献类型：
--
作者：
Christian G. Zoellin;H. Wunderlich;I. Polian;B. Becker
应在电路布局之前的早期设计步骤中针对软错误强化电路。以合理的成本实现软错误率 (SER) 降低的可行方法是仅强化电路的某些部分。在选择电路中要强化的位置时，应优先考虑错误可能导致系统故障的关键点。点的重要性取决于早期设计步骤中并非全部可用的参数。我们采用的选择策略仅考虑门级信息，不使用任何低级电气或时序信息。我们使用基于新的 UGC 粒子撞击模型的准确 SER 估计器来验证解决方案的质量。尽管仅利用部分信息进行强化，但精确的验证表明电路对软错误的敏感性显着降低。所提出的强化策略的结果在硬件开销和保护方面也优于已知的纯拓扑策略。
Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.