Clock period minimization of semi-synchronous circuits by gate-level delay insertion
Clock period minimization of semi-synchronous circuits by gate-level delay insertion
复制标题
通过门级延迟插入实现半同步电路时钟周期最小化
DOI：
10.1109/aspdac.1999.759775
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
Y. Kajitani
中科院分区：
文献类型：
--
作者：
T. Yoda;A. Takahashi;Y. Kajitani
半同步电路是一个电路，在该电路中，每个寄存器都会定期通过时钟勾选，但不一定同时勾选。半同步电路的一个特征是，相对于电路的时钟周期，寄存器之间的最小延迟可能至关重要。在本文中，我们讨论了一种延迟插入方法，该方法使这样的半同步电路更快。电路上循环的最大延迟注册比给出了时钟周期的下限。我们表明，在半同步框架中，通过提出的栅极级延迟插入方法在半同步框架中实现了这种结合，这是在电路上每个元素的延迟是唯一的。
A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio of the cycles on the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposed gate-level delay insertion method on the assumption that the delay of each element on the circuit is unique.