Recovery-driven design: A power minimization methodology for error-tolerant processor modules
Recovery-driven design: A power minimization methodology for error-tolerant processor modules
复制标题
恢复驱动设计：容错处理器模块的功耗最小化方法
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
J. Sartori
中科院分区：
文献类型：
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作者：
A. Kahng;Seokhyeong Kang;Rakesh Kumar;J. Sartori
传统的CAD方法优化处理器模块以进行正确的操作，并禁止在标称操作期间违反时序。在本文中，我们提出了恢复驱动设计，这是一种针对目标时序错误率而不是正确操作来优化处理器模块的设计方法。我们表明，恢复驱动的设计流程可以显著提高功率效益，该流程故意允许在额定工作期间发生电压超标引起的错误，同时依赖错误恢复技术来容忍这些错误。我们给出了这样一种CAD方法的详细评估和分析，该方法将处理器模块的功率最小化以达到目标错误率。在误码率分别为0.125%、0.25%、0.5%、1%、2%、4%和8%的情况下，与传统P&R相比，我们的功耗优势分别高达25%、19%、22%、24%、20%、28%和20%。将恢复驱动的设计与错误恢复技术相结合，可以提高效率并节省额外的电能。
Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timing violations during nominal operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings.