SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT
SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT
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SATSoT：一种使用 SAT 在常规结构上映射可控极性设备的方法
DOI：
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发表时间：
2013
期刊：
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通讯作者：
G. Micheli
中科院分区：
文献类型：
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作者：
Catherine Gasnier;P. Gaillardon;G. Micheli
具有可控极性的器件，如双栅垂直堆叠的纳米线FET，近年来在以前所未有的紧凑方式实现基于异或的逻辑功能方面表现出了巨大的兴趣。这种紧凑性是以更密集的互连为代价获得的，可以通过设计一种称为瓦海的高效超规则布局结构来缓解这种互连。在本文中，我们提出了一种基于布尔可满足性的方法来将晶体管网表映射到这样的结构上。该方法通过最大化不同端子的共享来努力将布线复杂性降至最低。我们展示了它的实现SATSoT能够自动生成具有类似于手动布局的连接复杂性的紧凑映射。
Devices with controllable-polarity, such as Double-Gate Vertically-Stacked Nanowire FETs, have shown promising interests in recent years to implement XOR-based logic functions in an unprecedented compact way. Such a compactness is obtained at the cost of a denser interconnect, that can be mitigated by designing an efficient hyper-regular layout structure, called Sea-of-Tiles. In this paper, we propose a methodology, based on Boolean satisfiability, to map netlists of transistors on such a structure. The methodology endeavors to minimize the wiring complexity, by maximizing the sharing of the different terminals. We showed that its implementation, SATSoT, is able to automatically generate compact mappings with wiring complexities similar to manual layouts.