Machine-Learning Based Delay Prediction for FPGA Technology Mapping
Machine-Learning Based Delay Prediction for FPGA Technology Mapping
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DOI：
10.1145/3557988.3569713
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发表时间：
2022-11
期刊：
影响因子：
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通讯作者：
Hailiang Hu;Jiang Hu;Fan Zhang;Binghe Tian;Ismail Bustany
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文献类型：
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作者：
Hailiang Hu;Jiang Hu;Fan Zhang;Binghe Tian;Ismail Bustany
准确的延迟预测在逻辑和高级综合的早期阶段非常重要。在现场可编程门阵列（FPGA）的技术映射中，门级电路被转录成查找表（LUT）级电路。在预映射电路上进行快速时序分析是必要的，以指导下游的优化。然而，静态时序分析由于其复杂性和高度不准确，与技术映射之前其他更快的经验启发式方法一样，速度太慢。在这项工作中，我们提出了一个基于机器学习的框架，通过预测技术映射后相应LUT逻辑的深度，准确有效地估计门级电路的延迟。实验结果表明，与现有的延迟估计启发式算法相比，该方法的准确率提高了56倍。我们的延迟估计器在运行时节省了87.5%的时间，误差可以忽略不计，而不是运行映射器。
Accurate delay prediction is important in the early stages of logic and high-level synthesis. In technology mapping for field programmable gate array (FPGA), a gate-level circuit is transcribed into a lookup table (LUT)-level circuit. Quick timing analysis is necessary on a pre-mapped circuit to guide optimizations downstream. However, a static timing analyzer is too slow due to its complexity and highly inaccurate like other faster empirical heuristics before technology mapping. In this work, we present a machine learning based framework for accurately and efficiently estimating the delay of a gate-level circuit from predicting the depth of the corresponding LUT logic after technology mapping. Our experimental results show that the proposed method achieves a 56x accuracy improvement compared to the existing delay estimation heuristic. Instead of running the mapper for the ground truth, our delay estimator saves 87.5% on runtime with negligible error.