Understanding the behavior and implications of context switch misses
Understanding the behavior and implications of context switch misses
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DOI：
10.1145/1880043.1880048
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发表时间：
2010-12
期刊：
影响因子：
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通讯作者：
Fang Liu;Yan Solihin
中科院分区：
文献类型：
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作者：
Fang Liu;Yan Solihin
现代计算机系统的基本特征之一是上下文切换，它允许多个执行线程在有限数量的处理器上分时执行。虽然非常有用，但上下文切换可能会引入高性能开销，其中一个主要原因是该高速缓存扰动效应。在线程被切换出的时间和它恢复执行的时间之间，它在该高速缓存中的工作集的部分可能被其他干扰线程扰乱，导致（上下文切换）高速缓存未命中从扰乱中恢复。本文的目标是了解缓存参数和应用程序行为如何影响应用程序遭受的上下文切换未命中的数量。我们描述了一个以前未报告的上下文切换未命中类型的缓存替换策略和应用程序的时间重用行为的相互作用的工件发生。我们的行为特征，这些“重新排序的失误”为各种应用程序，缓存大小，和各种数量的缓存扰动。作为第二个贡献，我们开发了一个分析模型，揭示了高速缓存设计参数之间的数学关系，应用程序的时间重用模式，和上下文切换未命中的应用程序遭受。我们验证了模型对模拟研究，并发现它是足够准确地预测上下文切换未命中的趋势方面的各种缓存扰动量。该模型提供的数学关系使我们能够准确地了解为什么某些应用程序比其他应用程序更容易受到上下文切换失误的影响。通过一个预取的案例研究，我们发现，预取往往会加剧上下文切换失误的数量和一个较小的聚合预取技术可以减少上下文切换失误的应用程序遭受的数量。我们还研究了缓存大小如何影响上下文切换失误。我们的研究表明，在系统中相对繁重的工作负载下，应用程序遭受的最坏情况下的上下文切换未命中的数量往往与缓存大小成比例地增加，在某种程度上，可能会完全否定其他类型的缓存未命中的减少。
One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very useful, context switching can introduce high performance overheads, with one of the primary reasons being the cache perturbation effect. Between the time a thread is switched out and when it resumes execution, parts of its working set in the cache may be perturbed by other interfering threads, leading to (context switch) cache misses to recover from the perturbation. The goal of this article is to understand how cache parameters and application behavior influence the number of context switch misses the application suffers from. We characterize a previously unreported type of context switch misses that occur as the artifact of the interaction of cache replacement policy and an application's temporal reuse behavior. We characterize the behavior of these “reordered misses” for various applications, cache sizes, and various amount of cache perturbation. As a second contribution, we develop an analytical model that reveals the mathematical relationship between cache design parameters, an application's temporal reuse pattern, and the number of context switch misses the application suffers from. We validate the model against simulation studies and find that it is sufficiently accurate in predicting the trends of context switch misses with regard to various cache perturbation amount. The mathematical relationship provided by the model allows us to derive insights into precisely why some applications are more vulnerable to context switch misses than others. Through a case study on prefetching, we find that prefetching tends to aggravate the number of context switch misses and a less aggresive prefetching technique can reduce the number of context switch misses the application suffers from. We also investigate how cache sizes affect context switch misses. Our study shows that under relatively heavy workloads in the system, the worst-case number of context switch misses an application suffers from tends to increase proportionally with cache sizes, to the extent that may completely negate the reduction in other types of cache misses.