A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes
A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes
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28.5 GB/s CMOS 无阻塞路由器，用于多个处理器和外围 I/O 节点之间的太比特/秒连接
DOI：
10.1109/isscc.2001.912614
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
Wilson
中科院分区：
文献类型：
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作者：
Chris;G. Dermer;Vasanlha Erragunlla;V. Govindarajulu;Amaresh Pangal;James;Prijic;Rankin;Erik Seligman;S. Vangal;Howard;Wilson
一台28.5 Gb/S数据路由器实现了太比特/S带宽网络。6.6M晶体管0.18/SPLµ/m 1.3 V 15 W CMOSLSI具有三个时钟域，通过四个1.06 Gb/S链路、一个B端口交叉开关和五个点对点链路进行数据同步，每个链路的数据吞吐量为4.75 Gb/S。测试数据速率高达每线6.4 GB/S。
A 28.5 GB/s data router enables a terabits/s bandwidth network. The 6.6M transistor 0.18 /spl mu/m 1.3 V 15 W CMOS LSI has three clocking domains that synchronize data through four 1.06 GB/s links, a B-port crossbar, and five point-to-point links of 4.75 GB/s data throughput each. Test data rates are up to 6.4 Gb/s per wire.