A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
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DOI：
10.1109/jssc.2016.2609386
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发表时间：
2017-01-01
影响因子：
5.4
通讯作者：
Choi, Jaeseung
中科院分区：
文献类型：
--
作者：
Song, Taejoong;Rim, Woojin;Choi, Jaeseung
两个 128 Mb 6T SRAM 测试芯片采用 10 nm FinFET 技术实现。 0.040 μ m(2) 6T SRAM 位单元专为高密度 (HD) 而设计，0.049 μ m(2) 则为高性能 (HP) 而设计。探索了各种 SRAM 辅助方案来评估功率、性能和面积 (PPA) 增益，并通过最小工作电压 (V-MIN) 和辅助开销得出品质因数 (FOM)。提出的双瞬态字线方案可将 128 Mb 6T-HP SRAM 的 V-MIN 提高 47.5 mV。具有负位线的抑制位线方案将 128 Mb 6T-HD SRAM 的 VMIN 提高了 135 mV。 PPA 增益的 FOM 根据应用评估不同位单元的最佳 SRAM 辅助。
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 mu m(2) 6T SRAM bitcell is designed for high density ( HD), and 0.049 mu m(2) for high performance ( HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area ( PPA) gain, and the figure-of-merit ( FOM) is induced by the minimum operating voltage ( V-MIN) and assist overheads. The dual-transient wordline scheme is proposed to improve the V-MIN by 47.5 mV for the 128 Mb 6T-HP SRAM. The suppressed bitline scheme with negative bitline improves the VMIN by 135 mV for the 128 Mb 6T-HD SRAM. The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications.