Accelerator design with decoupled hardware customizations: benefits and challenges: invited
Accelerator design with decoupled hardware customizations: benefits and challenges: invited
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DOI：
10.1145/3489517.3530681
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发表时间：
2022-07
期刊：
影响因子：
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通讯作者：
D. Pal;Yi-Hsiang Lai;Shaojie Xiang;Niansong Zhang;Hongzheng Chen;Jeremy Casas;P. Cocchini;Zhenkun Ya
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文献类型：
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作者：
D. Pal;Yi-Hsiang Lai;Shaojie Xiang;Niansong Zhang;Hongzheng Chen;Jeremy Casas;P. Cocchini;Zhenkun Ya
在过去的十年中，越来越多地采用了高级合成（HLS）来实施针对FPGA或ASIC的专业硬件加速器。但是，当前的HLS编程模型将算法规范与硬件自定义技术纠缠在一起，从而降低了加速器设计的生产率和可移植性。为了解决这个问题，诸如HeteroCl之类的最新努力提议将算法定义从计算，数据类型和内存中的基本硬件定制技术中解脱出来，从而提高生产率，可移植性和性能。尽管算法和自定义的解耦为编译/综合过程提供了好处，但它们还为程序员创造了新的障碍，以有效地调试并验证优化设计的正确性。在这项工作中，使用杂元和现实的机器学习应用程序作为案例研究，我们首先解释了向程序员带来的解耦编程模型的关键优势，以快速开发高性能加速器。使用相同的案例研究，我们将进一步展示看似良性的定制原始方法的良性使用情况如何导致验证的新挑战。然后，我们将概述研究机会，并讨论我们最近的一些努力，这是实现将来有强大且可行的验证解决方案的第一步。
The past decade has witnessed increasing adoption of high-level synthesis (HLS) to implement specialized hardware accelerators targeting either FPGAs or ASICs. However, current HLS programming models entangle algorithm specifications with hardware customization techniques, which lowers both the productivity and portability of the accelerator design. To tackle this problem, recent efforts such as HeteroCL propose to decouple algorithm definition from essential hardware customization techniques in compute, data type, and memory, increasing productivity, portability, and performance. While the decoupling of the algorithm and customizations provides benefits to the compilation/synthesis process, they also create new hurdles for the programmers to productively debug and validate the correctness of the optimized design. In this work, using HeteroCL and realistic machine learning applications as case studies, we first explain the key advantages of the decoupled programming model brought to a programmer to rapidly develop high-performance accelerators. Using the same case studies, we will further show how seemingly benign usage of the customization primitives can lead to new challenges to verification. We will then outline the research opportunities and discuss some of our recent efforts as the first step to enable a robust and viable verification solution in the future.