Advantages of heterogeneous logic block architecture for FPGAs
Advantages of heterogeneous logic block architecture for FPGAs
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FPGA 异构逻辑块架构的优势
DOI：
10.1109/cicc.1993.590578
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发表时间：
1993
期刊：
影响因子：
--
通讯作者：
Jonathan Rose
中科院分区：
文献类型：
--
作者：
Jian;Jonathan Rose
The authors consider field programmable gate arrays (FPGAs) that use two different sizes of lookup table (LUT) logic blocks and investigate the area-efficiency of different mixtures of different sizes of LUTs. Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs. A 6-LUT/4-LUT combination will likely exhibit better performance with nearly equivalent area than a homogeneous 4-LUT FPGA.
