Fast Polar Decoders: Algorithm and Implementation
Fast Polar Decoders: Algorithm and Implementation
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DOI：
10.1109/jsac.2014.140514
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发表时间：
2014-05-01
影响因子：
16.4
通讯作者：
Gross, Warren J.
中科院分区：
文献类型：
--
作者：
Sarkis, Gabi;Giard, Pascal;Gross, Warren J.
可以证明，极性码在具有显式结构的同时实现了无内存信道的对称容量。然而，极性码的采用一直受到其解码算法的低吞吐量的阻碍。这项工作旨在将极性解码硬件的吞吐量相对于连续消除解码器提高一个数量级，比目前最快的极性解码器快8倍以上。我们提出了一种算法，架构和FPGA实现的灵活的，千兆每秒极性解码器。
Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.