Compiling quantum circuits to realistic hardware architectures using temporal planners

Compiling quantum circuits to realistic hardware architectures using temporal planners
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DOI:
10.1088/2058-9565/aaa331
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发表时间:
2017-05
影响因子:
6.7
通讯作者:
D. Venturelli;M. Do;E. Rieffel;J. Frank
D. Venturelli;M. Do;E. Rieffel;J. Frank
中科院分区:
物理与天体物理1区
文献类型:
--
作者:
D. Venturelli;M. Do;E. Rieffel;J. Frank

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要在新兴的门模型量子硬件上运行量子算法,必须编译量子电路以考虑对硬件的限制。对于只有有限手段来缓解消相干的近期硬件而言,最大限度地减少电路的持续时间是至关重要的。我们研究了时间规划器在将量子电路编译成新出现的量子硬件问题上的应用。虽然我们的方法是通用的,但我们专注于编译成具有最近邻约束的超导硬件体系结构。我们最初的实验集中于编译量子交替运算符Anatz(QAOA)电路,其大量的整流门允许在门的应用顺序上具有极大的灵活性。这种自由度使寻找最优编译更具挑战性,但也意味着与灵活性较低的电路相比,更优化的编译具有更大的潜力。我们将量子电路编译问题映射为时间规划问题,并针对实际硬件架构生成了不同大小的QAOA电路编译问题的测试集。我们报告了几个最先进的时间规划者在这个测试集上的编译结果。这一早期的经验评估表明,时间规划是一种可行的量子电路编译方法。
To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.