Hardware accelerators for financial applications in HDL and High Level Synthesis
Hardware accelerators for financial applications in HDL and High Level Synthesis
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HDL 和高级综合金融应用的硬件加速器
DOI：
10.1109/samos.2017.8344641
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
D. Soudris
中科院分区：
文献类型：
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作者：
I. Stamoulias;C. Kachris;D. Soudris
许多金融应用程序（例如用于风险评估的应用程序）需要高性能和低延迟实施来维持需要处理的大量数据。本文介绍了一套用于风险评估的金融应用的高性能硬件加速器（Black & Scholes、Black-76 和 Binomial）。加速器使用 HDL (VHDL) 进行定点开发，并使用 HLS 语言进行浮点开发。高级综合 (HLS) 允许从原始遗留代码快速实现硬件加速器。 HLS 硬件加速器已通过 Xilinx SDAccel 框架映射到 PCIe FPGA (ADM-KU3) 板上，并在资源、性能和准确性方面进行了全面比较。性能评估表明，HLS 由于浮点可以实现更高的精度，但在 DSP 方面需要的资源数量增加了 20%，而在 HDL 中开发的定点实现可以在资源方面节省大量空间，但与软件代码相比精度有限。
Many financial applications, like the one used for risk valuation, need high performance and low latency implementations to sustain the high volume of data that need to be processed. This paper presents a suite of high performance hardware accelerators for financial applications used in risk valuation (Black & Scholes, Black-76 and Binomial). The accelerators are developed in fixed point using HDL (VHDL) and in floating point using HLS languages. High Level Synthesis (HLS) allows fast implementation of hardware accelerators from the original legacy codes. The HLS hardware accelerators have been mapped onto a PCIe FPGA (ADM-KU3) board, through the Xilinx SDAccel framework and a thorough comparison in terms of resources, performance and accuracy has been performed. The performance evaluation shows that HLS can achieve higher accuracy due to the floating point, but requires up to 20% higher number of resources in terms of DSPs while the fixed-point implementations developed in HDL can save significant space in terms of resources but with limited accuracy compared to the software code.