Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning
Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning
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等离子处理对栅极图案化过程中关键尺寸控制和线宽粗糙度转移的好处
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发表时间：
2013
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影响因子：
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通讯作者：
C. Verove
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作者：
L. Azarnouche;E. Pargon;K. Menguelti;M. Fouchier;O. Joubert;P. Gouraud;C. Verove
目前的工作重点是典型栅极堆叠图案化过程中的线宽粗糙度 (LWR) 转移和关键尺寸控制，并展示了在图案转移到栅极堆叠之前引入 193 nm 光刻胶处理以提高工艺性能的好处。两种研究处理（HBr 等离子体和真空紫外线 (VUV) 等离子体辐射）已在覆盖光刻胶薄膜和光刻胶图案上进行了测试，以突出固化光刻胶的蚀刻和粗糙化机制。两种处理都增强了暴露于用于打开 Si-ARC（硅抗反射涂层）层的碳氟等离子体蚀刻工艺的光致抗蚀剂的抗蚀刻性。固化光刻胶的耐蚀刻性的提高归因于光刻胶内氧含量的降低以及处理过程中由VUV辐射引起的交联现象。由于表面粗糙度的大小与蚀刻厚度直接相关，因此与参考光刻胶相比，蚀刻速度较慢的固化光刻胶在相同的处理时间内将形成较低的表面粗糙度。在 Si-ARC 等离子体蚀刻步骤中，通过临界尺寸原子力显微镜研究了沿图案侧壁的 LWR 演变。研究表明，LWR 在抗蚀剂图案的顶部退化，并沿着图案侧壁传播。然而，只要退化没有到达抗蚀剂和 Si-ARC 之间的界面，LWR 在 Si-ARC 蚀刻步骤期间就会降低。由于抗蚀剂预处理增强了 Si-ARC 蚀刻期间的抗蚀剂蚀刻耐受性，因此沿侧壁的 LWR 退化受到限制，从而最大限度地减少了 LWR 转移。通过临界尺寸扫描电子显微镜结合功率谱密度拟合方法对 LWR 进行光谱分析，可以解释等离子蚀刻后观察到的 LWR 降低。研究表明，粗糙度的高频和中频成分（周期性低于 200nm）在栅极图案化过程中并未完全转移，从而使每个等离子体步骤的 LWR 降低。
The present work focuses on the line width roughness (LWR) transfer and the critical dimension control during a typical gate stack patterning and shows the benefits of introducing 193 nm photoresist treatments before pattern transfer into the gate stack to improve process performance. The two investigated treatments (HBr plasma and vacuum ultra violet (VUV) plasma radiation) have been tested on both blanket photoresist films and resist patterns to highlight the etching and roughening mechanisms of cured resists. Both treatments reinforce the etch resistance of the photoresist exposed to fluorocarbon plasma etching process used to open the Si-ARC (silicon antireflective coating) layer. The etch resistance improvement of cured resists is attributed to both the decrease in oxygen content within the resist and the crosslinking phenomena caused by VUV radiation during the treatment. As the magnitude of the surface roughness is directly correlated to the etched thickness, cured resists, which are etched less rapidly, will develop a lower surface roughness for the same processing time compared to reference resists. The LWR evolution along the pattern sidewalls has been studied by critical dimension atomic force microscopy during the Si-ARC plasma etching step. The study shows that the LWR is degraded at the top of the resist pattern and propagates along the pattern sidewalls. However, as long as the degradation does not reach the interface between resist and Si-ARC, the LWR decreases during the Si-ARC etching step. As resist pretreatments reinforce the resist etch resistance during Si-ARC etching, the LWR degradation along the sidewalls is limited leading to minimized LWR transfer. The LWR decrease observed after plasma etching has been explained thanks to a spectral analysis of the LWR performed by critical dimension scanning electron microscopy combined with the power spectral density fitting method. The study shows that the high and medium frequency components of the roughness (periodicity below 200 nm) are not totally transferred during the gate patterning allowing a LWR decrease at each plasma step.