A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems
A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems
复制标题
基于 FPGA 的实时系统中动态部分重配置的控制器
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
J. Sparsø
中科院分区：
文献类型：
--
作者：
Luca Pezzarossa;Martin Schoeberl;J. Sparsø
在实时系统中，硬件加速器的使用可以导致最坏情况下的执行时间加速，简化其分析，并减少其悲观情绪。在使用FPGA技术时，可以使用动态部分重新配置(DPR)来最小化面积，只需加载任何给定时间点所需的加速器。由现场可编程门阵列供应商提供的DPR控制器满足了广泛的要求，并依靠软件来管理重新配置。此方法可能会导致重新配置速度较慢和无法预测的时间。本文介绍了一种专门为硬实时系统开发的开源DPR控制器，并结合面向实时应用的开源多核平台T-CREST进行了原型设计。该控制器使处理器能够以时间可预测的方式执行重新配置，并支持不同的操作模式。文中还给出了一个用于码流转换、压缩和重构时间分析的软件工具。根据硬件成本、操作频率、速度和比特流压缩比与重新配置时间的权衡来评估DPR控制器。文中还给出了一个简单的应用实例，展示了控制器的重构功能。
In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.