Test Point Placement to Simplify Fault Detection
Test Point Placement to Simplify Fault Detection
复制标题
测试点放置可简化故障检测
DOI:
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发表时间:
1974
影响因子:
3.7
通讯作者:
A. D. Friedman
中科院分区:
文献类型:
--
作者:
John P. Hayes;A. D. Friedman
The problem of selecting test points to reduce the number of tests for fault detection in combinational logic networks is examined. A method is presented for labeling the lines of a network. Procedures are described for obtaining a minimal labeling, i.e., one corresponding to a minimal set of tests, for fanout-free circuits and for a restricted class of circuits with fanout. Using these procedures, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks. Some difficulties associated with test point placement in general networks are pointed out. It is shown that the labeling approach is also applicable to the problem of selecting and placing control logic.