Current flattening circuit for DPA countermeasure
Current flattening circuit for DPA countermeasure
复制标题
用于 DPA 对策的电流平坦电路
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
C. Patel
中科院分区：
文献类型：
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作者：
Ekarat Laohavaleeson;C. Patel
在密码学应用中，芯片外看到的功耗变化是入侵者从系统获得秘密或密钥材料的丰富信息源。差分功耗分析（DPA）技术利用统计函数分析密码系统的功耗，提取密码系统的密钥。因此，需要屏蔽该边信道信息，以使得在安全系统上执行功率分析非常困难或实际上不可能。在这项工作中，我们提出了一个片上DPA对策解决方案，可以添加到现有的加密核心在最后的设计阶段，影响最小。该电路采用0.18µm工艺实现，详细的布局级仿真结果在本文中给出。该电路已被验证为工作在典型的，快速和慢速的工艺参数。
In cryptographic applications, power consumption variations seen off-chip are a rich source of information for intruders to obtain secret or keying materials from the system. Differential Power Analysis (DPA) technique uses statistical functions to analyze the power consumption and extracts the secret keys from the cipher systems. Consequently, this side-channel information needs to be masked to make it very difficult or practically impossible to perform power analysis on the secured system. In this work, we propose an on-chip DPA countermeasure solution that can be added to an existing cryptographic core at the final design stage with minimal impact. The circuit was implemented in 0.18µm process and the results from detailed layout level simulations are presented in this work. The circuit has been verified to work with typical, fast and slow process parameters.