Opportunistic write for fast and reliable STT-MRAM
Opportunistic write for fast and reliable STT-MRAM
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DOI：
10.23919/date.2017.7927049
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发表时间：
2017-03
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通讯作者：
Nour Sayed;Mojtaba Ebrahimi;R. Bishnoi;M. Tahoori
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文献类型：
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作者：
Nour Sayed;Mojtaba Ebrahimi;R. Bishnoi;M. Tahoori
由于自旋转移扭矩磁随机存取存储器(STT-MRAM)中位单元的随机切换行为，需要过大的写裕度来保证可接受的可靠性和成品率水平。这防止了STT-MRAM在诸如L1或L2高速缓存的快速存储器中的使用。STT-MRAM的过度写入裕度可以通过机会性写入(即，在所有位切换完成之前终止写入过程)和通过降低热稳定性因数来在很大程度上减少。具有未完成写入的位必须由稳健纠错码(ECC)处理。然而，这种编码方案具有相对较大的解码等待时间，这显著增加了总体读取等待时间。此外，热引起的固位故障可能会限制此类方案的适用性。在这篇文章中，我们利用了错误检测比纠正快得多的事实。因此，可以快速检测错误，并且可以在所有错误数据到达系统的关键部分(例如提交阶段或存储器端口)之前将其还原。我们还提供了一种自适应方法来管理运行时与温度相关的保留故障。因此，我们提出的方法能够将STT-MRAM技术用于快速缓存应用。
Due to the stochastic switching behavior of the bit-cell in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), an excessive write margin is required to guarantee an acceptable level of reliability and yield. This prevents the usage of STT-MRAM in fast memories such as L1 or L2 caches. The excessive write margin of STT-MRAM can be reduced to a large extent by an opportunistic write (i.e., terminating the write process before all bit switchings are completed) and by reducing thermal stability factor. The bits with unfinished writes have to be processed by robust Error Correction Codes (ECCs). However, such coding schemes have relatively large decoding latencies, which increases the overall read latency significantly. Moreover, thermally induced retention failures can limit the applicability of such schemes. In this paper, we exploit the fact that error detection is much faster than correction. Therefore, the errors can be detected quickly and all erroneous data can be reverted before they arrive critical parts of the system (e.g., commit stage or memory ports). We also provide an adaptive approach to manage temperature-dependent retention failures at runtime. Hence, our proposed approach enables the use of STT-MRAM technology for fast cache applications.