Architectural synthesis of timed asynchronous systems
Architectural synthesis of timed asynchronous systems
复制标题
定时异步系统的架构综合
DOI：
10.1109/iccd.1999.808566
复制
发表时间：
1999
期刊：
影响因子：
--
通讯作者：
C. Myers
中科院分区：
文献类型：
--
作者：
Brandon M. Bachman;Hao Zheng;C. Myers
描述了一种用于定时异步系统的体系结构综合的新方法。由于与异步资源相关的可变延迟，隐式调度是通过在资源之间添加补充约束来创建的。由于调度的数量相对于给定数据流图的大小呈指数增长，因此引入了剪枝技术，该技术在不显著影响结果质量的情况下显著改善了运行时间。使用数据和资源约束的组合，以及对有限延迟信息的分析，我们的方法确定了实现给定调度所需的最小资源和寄存器数量。利用一些高级综合基准电路和一个工业实例对结果进行了验证。
Describes a new method for the architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponentially with respect to the size of the given data flow graph, pruning techniques are introduced which dramatically improve the run-time without significantly affecting the quality of the results. Using a combination of data and resource constraints, as well as an analysis of bounded delay information, our method determines the minimum number of resources and registers needed to implement a given schedule. Results are demonstrated using some high-level synthesis benchmark circuits and an industrial example.