Efficient Cache Architecture for Packet Processing in Internet Routers
Efficient Cache Architecture for Packet Processing in Internet Routers
复制标题
DOI：
10.1007/978-3-030-39445-5_26
复制
发表时间：
2020-03
期刊：
影响因子：
--
通讯作者：
Hayato Yamaki
中科院分区：
文献类型：
--
作者：
Hayato Yamaki
随着网络流量的不断增长，路由器在数据包处理吞吐量和功耗方面都面临着严重的问题。分组处理缓存（PPC）是解决这一问题的有效方法之一。PPC高速缓存表查找导致分组处理，并且能够减少TCAM（三元内容可寻址存储器）访问的次数，TCAM访问被认为是降低分组处理的吞吐量和功率效率的主要原因。虽然PPC可以在数据包命中该高速缓存的情况下以显著低的能量快速处理数据包，但是由于小的缓存容量，PPC的该高速缓存未命中率仍然很高。此外，由于传统PPC对攻击没有容忍度，因此当攻击时，PPC的该高速缓存未命中率急剧增加。针对这些问题，我们提出了两种不同的缓存架构，称为端口感知缓存和受害者IP缓存。我们的模拟表明，与传统PPC相比，它们的组合可以实现1.81倍的吞吐量，每包能量减少45%。
Recent internet traffic growth becomes a serious problem for internet routers from the aspects of both packet processing throughput and power consumption. Packet Processing Cache (PPC) is one of the promising approaches to solve this problem. PPC caches table lookup results in packet processing and enables to reduce the number of TCAM (Ternary Content Addressable Memory) accesses, which are known as the major cause of degrading the throughput and power efficiency of packet processing. Although PPC can process a packet at fast with significant low energy if the packet hits in the cache, the cache miss rate of PPC is still high due to the small cache capacity. Furthermore, because conventional PPC has no tolerance to attacks, the cache miss rate of PPC is drastically increased when attacking. For these problems, we propose two different cache architecture, called Port-aware Cache and Victim IP Cache. Our simulation showed that the combination of them can achieve 1.81x higher throughput with 45% smaller energy per packet when compared to conventional PPC.